
aoe:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400578 <_init>:
  400578:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40057c:	910003fd 	mov	x29, sp
  400580:	9400003e 	bl	400678 <call_weak_fn>
  400584:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400588:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400590 <.plt>:
  400590:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400594:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0x10184>
  400598:	f947fe11 	ldr	x17, [x16, #4088]
  40059c:	913fe210 	add	x16, x16, #0xff8
  4005a0:	d61f0220 	br	x17
  4005a4:	d503201f 	nop
  4005a8:	d503201f 	nop
  4005ac:	d503201f 	nop

00000000004005b0 <malloc@plt>:
  4005b0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005b4:	f9400211 	ldr	x17, [x16]
  4005b8:	91000210 	add	x16, x16, #0x0
  4005bc:	d61f0220 	br	x17

00000000004005c0 <__libc_start_main@plt>:
  4005c0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005c4:	f9400611 	ldr	x17, [x16, #8]
  4005c8:	91002210 	add	x16, x16, #0x8
  4005cc:	d61f0220 	br	x17

00000000004005d0 <__gmon_start__@plt>:
  4005d0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005d4:	f9400a11 	ldr	x17, [x16, #16]
  4005d8:	91004210 	add	x16, x16, #0x10
  4005dc:	d61f0220 	br	x17

00000000004005e0 <abort@plt>:
  4005e0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005e4:	f9400e11 	ldr	x17, [x16, #24]
  4005e8:	91006210 	add	x16, x16, #0x18
  4005ec:	d61f0220 	br	x17

00000000004005f0 <puts@plt>:
  4005f0:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  4005f4:	f9401211 	ldr	x17, [x16, #32]
  4005f8:	91008210 	add	x16, x16, #0x20
  4005fc:	d61f0220 	br	x17

0000000000400600 <__isoc99_scanf@plt>:
  400600:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  400604:	f9401611 	ldr	x17, [x16, #40]
  400608:	9100a210 	add	x16, x16, #0x28
  40060c:	d61f0220 	br	x17

0000000000400610 <printf@plt>:
  400610:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  400614:	f9401a11 	ldr	x17, [x16, #48]
  400618:	9100c210 	add	x16, x16, #0x30
  40061c:	d61f0220 	br	x17

0000000000400620 <putchar@plt>:
  400620:	d0000090 	adrp	x16, 412000 <malloc@GLIBC_2.17>
  400624:	f9401e11 	ldr	x17, [x16, #56]
  400628:	9100e210 	add	x16, x16, #0x38
  40062c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400630 <_start>:
  400630:	d280001d 	mov	x29, #0x0                   	// #0
  400634:	d280001e 	mov	x30, #0x0                   	// #0
  400638:	aa0003e5 	mov	x5, x0
  40063c:	f94003e1 	ldr	x1, [sp]
  400640:	910023e2 	add	x2, sp, #0x8
  400644:	910003e6 	mov	x6, sp
  400648:	580000c0 	ldr	x0, 400660 <_start+0x30>
  40064c:	580000e3 	ldr	x3, 400668 <_start+0x38>
  400650:	58000104 	ldr	x4, 400670 <_start+0x40>
  400654:	97ffffdb 	bl	4005c0 <__libc_start_main@plt>
  400658:	97ffffe2 	bl	4005e0 <abort@plt>
  40065c:	00000000 	.inst	0x00000000 ; undefined
  400660:	00400d40 	.word	0x00400d40
  400664:	00000000 	.word	0x00000000
  400668:	00400d78 	.word	0x00400d78
  40066c:	00000000 	.word	0x00000000
  400670:	00400df8 	.word	0x00400df8
  400674:	00000000 	.word	0x00000000

0000000000400678 <call_weak_fn>:
  400678:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0x10184>
  40067c:	f947f000 	ldr	x0, [x0, #4064]
  400680:	b4000040 	cbz	x0, 400688 <call_weak_fn+0x10>
  400684:	17ffffd3 	b	4005d0 <__gmon_start__@plt>
  400688:	d65f03c0 	ret
  40068c:	00000000 	.inst	0x00000000 ; undefined

0000000000400690 <deregister_tm_clones>:
  400690:	d0000080 	adrp	x0, 412000 <malloc@GLIBC_2.17>
  400694:	91014000 	add	x0, x0, #0x50
  400698:	d0000081 	adrp	x1, 412000 <malloc@GLIBC_2.17>
  40069c:	91014021 	add	x1, x1, #0x50
  4006a0:	eb00003f 	cmp	x1, x0
  4006a4:	540000a0 	b.eq	4006b8 <deregister_tm_clones+0x28>  // b.none
  4006a8:	90000001 	adrp	x1, 400000 <_init-0x578>
  4006ac:	f9470c21 	ldr	x1, [x1, #3608]
  4006b0:	b4000041 	cbz	x1, 4006b8 <deregister_tm_clones+0x28>
  4006b4:	d61f0020 	br	x1
  4006b8:	d65f03c0 	ret
  4006bc:	d503201f 	nop

00000000004006c0 <register_tm_clones>:
  4006c0:	d0000080 	adrp	x0, 412000 <malloc@GLIBC_2.17>
  4006c4:	91014000 	add	x0, x0, #0x50
  4006c8:	d0000081 	adrp	x1, 412000 <malloc@GLIBC_2.17>
  4006cc:	91014021 	add	x1, x1, #0x50
  4006d0:	cb000021 	sub	x1, x1, x0
  4006d4:	9343fc21 	asr	x1, x1, #3
  4006d8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4006dc:	9341fc21 	asr	x1, x1, #1
  4006e0:	b40000a1 	cbz	x1, 4006f4 <register_tm_clones+0x34>
  4006e4:	90000002 	adrp	x2, 400000 <_init-0x578>
  4006e8:	f9471042 	ldr	x2, [x2, #3616]
  4006ec:	b4000042 	cbz	x2, 4006f4 <register_tm_clones+0x34>
  4006f0:	d61f0040 	br	x2
  4006f4:	d65f03c0 	ret

00000000004006f8 <__do_global_dtors_aux>:
  4006f8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4006fc:	910003fd 	mov	x29, sp
  400700:	f9000bf3 	str	x19, [sp, #16]
  400704:	d0000093 	adrp	x19, 412000 <malloc@GLIBC_2.17>
  400708:	39414260 	ldrb	w0, [x19, #80]
  40070c:	35000080 	cbnz	w0, 40071c <__do_global_dtors_aux+0x24>
  400710:	97ffffe0 	bl	400690 <deregister_tm_clones>
  400714:	52800020 	mov	w0, #0x1                   	// #1
  400718:	39014260 	strb	w0, [x19, #80]
  40071c:	f9400bf3 	ldr	x19, [sp, #16]
  400720:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400724:	d65f03c0 	ret

0000000000400728 <frame_dummy>:
  400728:	17ffffe6 	b	4006c0 <register_tm_clones>

000000000040072c <adjacency>:
  40072c:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400730:	910003fd 	mov	x29, sp
  400734:	f9000fa0 	str	x0, [x29, #24]
  400738:	52800020 	mov	w0, #0x1                   	// #1
  40073c:	b9002fa0 	str	w0, [x29, #44]
  400740:	14000019 	b	4007a4 <adjacency+0x78>
  400744:	b9402fa0 	ldr	w0, [x29, #44]
  400748:	f9400fa1 	ldr	x1, [x29, #24]
  40074c:	93407c00 	sxtw	x0, w0
  400750:	9100dc00 	add	x0, x0, #0x37
  400754:	d37cec00 	lsl	x0, x0, #4
  400758:	8b000020 	add	x0, x1, x0
  40075c:	b900081f 	str	wzr, [x0, #8]
  400760:	b9402fa0 	ldr	w0, [x29, #44]
  400764:	f9400fa1 	ldr	x1, [x29, #24]
  400768:	93407c00 	sxtw	x0, w0
  40076c:	9100dc00 	add	x0, x0, #0x37
  400770:	d37cec00 	lsl	x0, x0, #4
  400774:	8b000020 	add	x0, x1, x0
  400778:	f900081f 	str	xzr, [x0, #16]
  40077c:	b9402fa0 	ldr	w0, [x29, #44]
  400780:	f9400fa1 	ldr	x1, [x29, #24]
  400784:	93407c00 	sxtw	x0, w0
  400788:	9100dc00 	add	x0, x0, #0x37
  40078c:	d37cec00 	lsl	x0, x0, #4
  400790:	8b000020 	add	x0, x1, x0
  400794:	b9000c1f 	str	wzr, [x0, #12]
  400798:	b9402fa0 	ldr	w0, [x29, #44]
  40079c:	11000400 	add	w0, w0, #0x1
  4007a0:	b9002fa0 	str	w0, [x29, #44]
  4007a4:	b9402fa0 	ldr	w0, [x29, #44]
  4007a8:	7100241f 	cmp	w0, #0x9
  4007ac:	54fffccd 	b.le	400744 <adjacency+0x18>
  4007b0:	52800020 	mov	w0, #0x1                   	// #1
  4007b4:	b9003fa0 	str	w0, [x29, #60]
  4007b8:	14000035 	b	40088c <adjacency+0x160>
  4007bc:	90000000 	adrp	x0, 400000 <_init-0x578>
  4007c0:	9138a000 	add	x0, x0, #0xe28
  4007c4:	97ffff8b 	bl	4005f0 <puts@plt>
  4007c8:	910093a3 	add	x3, x29, #0x24
  4007cc:	9100a3a2 	add	x2, x29, #0x28
  4007d0:	9100b3a1 	add	x1, x29, #0x2c
  4007d4:	90000000 	adrp	x0, 400000 <_init-0x578>
  4007d8:	9138e000 	add	x0, x0, #0xe38
  4007dc:	97ffff89 	bl	400600 <__isoc99_scanf@plt>
  4007e0:	d2800200 	mov	x0, #0x10                  	// #16
  4007e4:	97ffff73 	bl	4005b0 <malloc@plt>
  4007e8:	f9001ba0 	str	x0, [x29, #48]
  4007ec:	b9402ba1 	ldr	w1, [x29, #40]
  4007f0:	f9401ba0 	ldr	x0, [x29, #48]
  4007f4:	b9000001 	str	w1, [x0]
  4007f8:	b94027a1 	ldr	w1, [x29, #36]
  4007fc:	f9401ba0 	ldr	x0, [x29, #48]
  400800:	b9000401 	str	w1, [x0, #4]
  400804:	b9402fa0 	ldr	w0, [x29, #44]
  400808:	f9400fa1 	ldr	x1, [x29, #24]
  40080c:	93407c00 	sxtw	x0, w0
  400810:	9100dc00 	add	x0, x0, #0x37
  400814:	d37cec00 	lsl	x0, x0, #4
  400818:	8b000020 	add	x0, x1, x0
  40081c:	f9400801 	ldr	x1, [x0, #16]
  400820:	f9401ba0 	ldr	x0, [x29, #48]
  400824:	f9000401 	str	x1, [x0, #8]
  400828:	b9402fa0 	ldr	w0, [x29, #44]
  40082c:	f9400fa1 	ldr	x1, [x29, #24]
  400830:	93407c00 	sxtw	x0, w0
  400834:	9100dc00 	add	x0, x0, #0x37
  400838:	d37cec00 	lsl	x0, x0, #4
  40083c:	8b000020 	add	x0, x1, x0
  400840:	f9401ba1 	ldr	x1, [x29, #48]
  400844:	f9000801 	str	x1, [x0, #16]
  400848:	b9402fa3 	ldr	w3, [x29, #44]
  40084c:	f9400fa1 	ldr	x1, [x29, #24]
  400850:	93407c60 	sxtw	x0, w3
  400854:	9100dc00 	add	x0, x0, #0x37
  400858:	d37cec00 	lsl	x0, x0, #4
  40085c:	8b000020 	add	x0, x1, x0
  400860:	b9400800 	ldr	w0, [x0, #8]
  400864:	11000401 	add	w1, w0, #0x1
  400868:	f9400fa2 	ldr	x2, [x29, #24]
  40086c:	93407c60 	sxtw	x0, w3
  400870:	9100dc00 	add	x0, x0, #0x37
  400874:	d37cec00 	lsl	x0, x0, #4
  400878:	8b000040 	add	x0, x2, x0
  40087c:	b9000801 	str	w1, [x0, #8]
  400880:	b9403fa0 	ldr	w0, [x29, #60]
  400884:	11000400 	add	w0, w0, #0x1
  400888:	b9003fa0 	str	w0, [x29, #60]
  40088c:	b9403fa0 	ldr	w0, [x29, #60]
  400890:	71002c1f 	cmp	w0, #0xb
  400894:	54fff94d 	b.le	4007bc <adjacency+0x90>
  400898:	d503201f 	nop
  40089c:	a8c47bfd 	ldp	x29, x30, [sp], #64
  4008a0:	d65f03c0 	ret

00000000004008a4 <topsort>:
  4008a4:	d100c3ff 	sub	sp, sp, #0x30
  4008a8:	f90007e0 	str	x0, [sp, #8]
  4008ac:	b9002fff 	str	wzr, [sp, #44]
  4008b0:	f94007e0 	ldr	x0, [sp, #8]
  4008b4:	b903701f 	str	wzr, [x0, #880]
  4008b8:	f94007e0 	ldr	x0, [sp, #8]
  4008bc:	b903741f 	str	wzr, [x0, #884]
  4008c0:	52800020 	mov	w0, #0x1                   	// #1
  4008c4:	b90027e0 	str	w0, [sp, #36]
  4008c8:	14000007 	b	4008e4 <topsort+0x40>
  4008cc:	f94007e0 	ldr	x0, [sp, #8]
  4008d0:	b98027e1 	ldrsw	x1, [sp, #36]
  4008d4:	b821781f 	str	wzr, [x0, x1, lsl #2]
  4008d8:	b94027e0 	ldr	w0, [sp, #36]
  4008dc:	11000400 	add	w0, w0, #0x1
  4008e0:	b90027e0 	str	w0, [sp, #36]
  4008e4:	b94027e0 	ldr	w0, [sp, #36]
  4008e8:	7100241f 	cmp	w0, #0x9
  4008ec:	54ffff0d 	b.le	4008cc <topsort+0x28>
  4008f0:	52800020 	mov	w0, #0x1                   	// #1
  4008f4:	b9002be0 	str	w0, [sp, #40]
  4008f8:	14000018 	b	400958 <topsort+0xb4>
  4008fc:	f94007e1 	ldr	x1, [sp, #8]
  400900:	b9802be0 	ldrsw	x0, [sp, #40]
  400904:	9100dc00 	add	x0, x0, #0x37
  400908:	d37cec00 	lsl	x0, x0, #4
  40090c:	8b000020 	add	x0, x1, x0
  400910:	b9400800 	ldr	w0, [x0, #8]
  400914:	7100001f 	cmp	w0, #0x0
  400918:	540001a1 	b.ne	40094c <topsort+0xa8>  // b.any
  40091c:	f94007e0 	ldr	x0, [sp, #8]
  400920:	b9437000 	ldr	w0, [x0, #880]
  400924:	11000401 	add	w1, w0, #0x1
  400928:	f94007e0 	ldr	x0, [sp, #8]
  40092c:	b9037001 	str	w1, [x0, #880]
  400930:	f94007e0 	ldr	x0, [sp, #8]
  400934:	b9437001 	ldr	w1, [x0, #880]
  400938:	f94007e0 	ldr	x0, [sp, #8]
  40093c:	93407c21 	sxtw	x1, w1
  400940:	91005021 	add	x1, x1, #0x14
  400944:	b9402be2 	ldr	w2, [sp, #40]
  400948:	b8217802 	str	w2, [x0, x1, lsl #2]
  40094c:	b9402be0 	ldr	w0, [sp, #40]
  400950:	11000400 	add	w0, w0, #0x1
  400954:	b9002be0 	str	w0, [sp, #40]
  400958:	b9402be0 	ldr	w0, [sp, #40]
  40095c:	7100241f 	cmp	w0, #0x9
  400960:	54fffced 	b.le	4008fc <topsort+0x58>
  400964:	14000060 	b	400ae4 <topsort+0x240>
  400968:	f94007e0 	ldr	x0, [sp, #8]
  40096c:	b9437000 	ldr	w0, [x0, #880]
  400970:	51000402 	sub	w2, w0, #0x1
  400974:	f94007e1 	ldr	x1, [sp, #8]
  400978:	b9037022 	str	w2, [x1, #880]
  40097c:	f94007e1 	ldr	x1, [sp, #8]
  400980:	93407c00 	sxtw	x0, w0
  400984:	91005000 	add	x0, x0, #0x14
  400988:	b8607820 	ldr	w0, [x1, x0, lsl #2]
  40098c:	b90017e0 	str	w0, [sp, #20]
  400990:	f94007e0 	ldr	x0, [sp, #8]
  400994:	b9437400 	ldr	w0, [x0, #884]
  400998:	11000401 	add	w1, w0, #0x1
  40099c:	f94007e0 	ldr	x0, [sp, #8]
  4009a0:	b9037401 	str	w1, [x0, #884]
  4009a4:	f94007e0 	ldr	x0, [sp, #8]
  4009a8:	b9437401 	ldr	w1, [x0, #884]
  4009ac:	f94007e0 	ldr	x0, [sp, #8]
  4009b0:	93407c21 	sxtw	x1, w1
  4009b4:	9101e021 	add	x1, x1, #0x78
  4009b8:	b94017e2 	ldr	w2, [sp, #20]
  4009bc:	b8217802 	str	w2, [x0, x1, lsl #2]
  4009c0:	b9402fe0 	ldr	w0, [sp, #44]
  4009c4:	11000400 	add	w0, w0, #0x1
  4009c8:	b9002fe0 	str	w0, [sp, #44]
  4009cc:	f94007e1 	ldr	x1, [sp, #8]
  4009d0:	b98017e0 	ldrsw	x0, [sp, #20]
  4009d4:	9100dc00 	add	x0, x0, #0x37
  4009d8:	d37cec00 	lsl	x0, x0, #4
  4009dc:	8b000020 	add	x0, x1, x0
  4009e0:	f9400800 	ldr	x0, [x0, #16]
  4009e4:	f9000fe0 	str	x0, [sp, #24]
  4009e8:	1400003c 	b	400ad8 <topsort+0x234>
  4009ec:	f9400fe0 	ldr	x0, [sp, #24]
  4009f0:	b9400000 	ldr	w0, [x0]
  4009f4:	b90013e0 	str	w0, [sp, #16]
  4009f8:	f94007e1 	ldr	x1, [sp, #8]
  4009fc:	b98013e0 	ldrsw	x0, [sp, #16]
  400a00:	9100dc00 	add	x0, x0, #0x37
  400a04:	d37cec00 	lsl	x0, x0, #4
  400a08:	8b000020 	add	x0, x1, x0
  400a0c:	b9400800 	ldr	w0, [x0, #8]
  400a10:	51000401 	sub	w1, w0, #0x1
  400a14:	f94007e2 	ldr	x2, [sp, #8]
  400a18:	b98013e0 	ldrsw	x0, [sp, #16]
  400a1c:	9100dc00 	add	x0, x0, #0x37
  400a20:	d37cec00 	lsl	x0, x0, #4
  400a24:	8b000040 	add	x0, x2, x0
  400a28:	b9000801 	str	w1, [x0, #8]
  400a2c:	f94007e1 	ldr	x1, [sp, #8]
  400a30:	b98013e0 	ldrsw	x0, [sp, #16]
  400a34:	9100dc00 	add	x0, x0, #0x37
  400a38:	d37cec00 	lsl	x0, x0, #4
  400a3c:	8b000020 	add	x0, x1, x0
  400a40:	b9400800 	ldr	w0, [x0, #8]
  400a44:	7100001f 	cmp	w0, #0x0
  400a48:	540001a1 	b.ne	400a7c <topsort+0x1d8>  // b.any
  400a4c:	f94007e0 	ldr	x0, [sp, #8]
  400a50:	b9437000 	ldr	w0, [x0, #880]
  400a54:	11000401 	add	w1, w0, #0x1
  400a58:	f94007e0 	ldr	x0, [sp, #8]
  400a5c:	b9037001 	str	w1, [x0, #880]
  400a60:	f94007e0 	ldr	x0, [sp, #8]
  400a64:	b9437001 	ldr	w1, [x0, #880]
  400a68:	f94007e0 	ldr	x0, [sp, #8]
  400a6c:	93407c21 	sxtw	x1, w1
  400a70:	91005021 	add	x1, x1, #0x14
  400a74:	b94013e2 	ldr	w2, [sp, #16]
  400a78:	b8217802 	str	w2, [x0, x1, lsl #2]
  400a7c:	f94007e0 	ldr	x0, [sp, #8]
  400a80:	b98017e1 	ldrsw	x1, [sp, #20]
  400a84:	b8617801 	ldr	w1, [x0, x1, lsl #2]
  400a88:	f9400fe0 	ldr	x0, [sp, #24]
  400a8c:	b9400400 	ldr	w0, [x0, #4]
  400a90:	0b000021 	add	w1, w1, w0
  400a94:	f94007e0 	ldr	x0, [sp, #8]
  400a98:	b98013e2 	ldrsw	x2, [sp, #16]
  400a9c:	b8627800 	ldr	w0, [x0, x2, lsl #2]
  400aa0:	6b00003f 	cmp	w1, w0
  400aa4:	5400014d 	b.le	400acc <topsort+0x228>
  400aa8:	f94007e0 	ldr	x0, [sp, #8]
  400aac:	b98017e1 	ldrsw	x1, [sp, #20]
  400ab0:	b8617801 	ldr	w1, [x0, x1, lsl #2]
  400ab4:	f9400fe0 	ldr	x0, [sp, #24]
  400ab8:	b9400400 	ldr	w0, [x0, #4]
  400abc:	0b000022 	add	w2, w1, w0
  400ac0:	f94007e0 	ldr	x0, [sp, #8]
  400ac4:	b98013e1 	ldrsw	x1, [sp, #16]
  400ac8:	b8217802 	str	w2, [x0, x1, lsl #2]
  400acc:	f9400fe0 	ldr	x0, [sp, #24]
  400ad0:	f9400400 	ldr	x0, [x0, #8]
  400ad4:	f9000fe0 	str	x0, [sp, #24]
  400ad8:	f9400fe0 	ldr	x0, [sp, #24]
  400adc:	f100001f 	cmp	x0, #0x0
  400ae0:	54fff861 	b.ne	4009ec <topsort+0x148>  // b.any
  400ae4:	f94007e0 	ldr	x0, [sp, #8]
  400ae8:	b9437000 	ldr	w0, [x0, #880]
  400aec:	7100001f 	cmp	w0, #0x0
  400af0:	54fff3cc 	b.gt	400968 <topsort+0xc4>
  400af4:	d503201f 	nop
  400af8:	9100c3ff 	add	sp, sp, #0x30
  400afc:	d65f03c0 	ret

0000000000400b00 <critical_path>:
  400b00:	a9bb7bfd 	stp	x29, x30, [sp, #-80]!
  400b04:	910003fd 	mov	x29, sp
  400b08:	f9000fa0 	str	x0, [x29, #24]
  400b0c:	52800020 	mov	w0, #0x1                   	// #1
  400b10:	b9003fa0 	str	w0, [x29, #60]
  400b14:	1400000c 	b	400b44 <critical_path+0x44>
  400b18:	f9400fa0 	ldr	x0, [x29, #24]
  400b1c:	b9402401 	ldr	w1, [x0, #36]
  400b20:	f9400fa2 	ldr	x2, [x29, #24]
  400b24:	b9803fa0 	ldrsw	x0, [x29, #60]
  400b28:	91002000 	add	x0, x0, #0x8
  400b2c:	d37ef400 	lsl	x0, x0, #2
  400b30:	8b000040 	add	x0, x2, x0
  400b34:	b9000801 	str	w1, [x0, #8]
  400b38:	b9403fa0 	ldr	w0, [x29, #60]
  400b3c:	11000400 	add	w0, w0, #0x1
  400b40:	b9003fa0 	str	w0, [x29, #60]
  400b44:	b9403fa0 	ldr	w0, [x29, #60]
  400b48:	7100241f 	cmp	w0, #0x9
  400b4c:	54fffe6d 	b.le	400b18 <critical_path+0x18>
  400b50:	1400003d 	b	400c44 <critical_path+0x144>
  400b54:	f9400fa0 	ldr	x0, [x29, #24]
  400b58:	b9437400 	ldr	w0, [x0, #884]
  400b5c:	51000402 	sub	w2, w0, #0x1
  400b60:	f9400fa1 	ldr	x1, [x29, #24]
  400b64:	b9037422 	str	w2, [x1, #884]
  400b68:	f9400fa1 	ldr	x1, [x29, #24]
  400b6c:	93407c00 	sxtw	x0, w0
  400b70:	9101e000 	add	x0, x0, #0x78
  400b74:	b8607820 	ldr	w0, [x1, x0, lsl #2]
  400b78:	b9004fa0 	str	w0, [x29, #76]
  400b7c:	f9400fa1 	ldr	x1, [x29, #24]
  400b80:	b9804fa0 	ldrsw	x0, [x29, #76]
  400b84:	9100dc00 	add	x0, x0, #0x37
  400b88:	d37cec00 	lsl	x0, x0, #4
  400b8c:	8b000020 	add	x0, x1, x0
  400b90:	f9400800 	ldr	x0, [x0, #16]
  400b94:	f90023a0 	str	x0, [x29, #64]
  400b98:	14000028 	b	400c38 <critical_path+0x138>
  400b9c:	f94023a0 	ldr	x0, [x29, #64]
  400ba0:	b9400000 	ldr	w0, [x0]
  400ba4:	b9003ba0 	str	w0, [x29, #56]
  400ba8:	f94023a0 	ldr	x0, [x29, #64]
  400bac:	b9400400 	ldr	w0, [x0, #4]
  400bb0:	b90037a0 	str	w0, [x29, #52]
  400bb4:	f9400fa1 	ldr	x1, [x29, #24]
  400bb8:	b9803ba0 	ldrsw	x0, [x29, #56]
  400bbc:	91002000 	add	x0, x0, #0x8
  400bc0:	d37ef400 	lsl	x0, x0, #2
  400bc4:	8b000020 	add	x0, x1, x0
  400bc8:	b9400801 	ldr	w1, [x0, #8]
  400bcc:	b94037a0 	ldr	w0, [x29, #52]
  400bd0:	4b000021 	sub	w1, w1, w0
  400bd4:	f9400fa2 	ldr	x2, [x29, #24]
  400bd8:	b9804fa0 	ldrsw	x0, [x29, #76]
  400bdc:	91002000 	add	x0, x0, #0x8
  400be0:	d37ef400 	lsl	x0, x0, #2
  400be4:	8b000040 	add	x0, x2, x0
  400be8:	b9400800 	ldr	w0, [x0, #8]
  400bec:	6b00003f 	cmp	w1, w0
  400bf0:	540001ea 	b.ge	400c2c <critical_path+0x12c>  // b.tcont
  400bf4:	f9400fa1 	ldr	x1, [x29, #24]
  400bf8:	b9803ba0 	ldrsw	x0, [x29, #56]
  400bfc:	91002000 	add	x0, x0, #0x8
  400c00:	d37ef400 	lsl	x0, x0, #2
  400c04:	8b000020 	add	x0, x1, x0
  400c08:	b9400801 	ldr	w1, [x0, #8]
  400c0c:	b94037a0 	ldr	w0, [x29, #52]
  400c10:	4b000021 	sub	w1, w1, w0
  400c14:	f9400fa2 	ldr	x2, [x29, #24]
  400c18:	b9804fa0 	ldrsw	x0, [x29, #76]
  400c1c:	91002000 	add	x0, x0, #0x8
  400c20:	d37ef400 	lsl	x0, x0, #2
  400c24:	8b000040 	add	x0, x2, x0
  400c28:	b9000801 	str	w1, [x0, #8]
  400c2c:	f94023a0 	ldr	x0, [x29, #64]
  400c30:	f9400400 	ldr	x0, [x0, #8]
  400c34:	f90023a0 	str	x0, [x29, #64]
  400c38:	f94023a0 	ldr	x0, [x29, #64]
  400c3c:	f100001f 	cmp	x0, #0x0
  400c40:	54fffae1 	b.ne	400b9c <critical_path+0x9c>  // b.any
  400c44:	f9400fa0 	ldr	x0, [x29, #24]
  400c48:	b9437400 	ldr	w0, [x0, #884]
  400c4c:	7100001f 	cmp	w0, #0x0
  400c50:	54fff82c 	b.gt	400b54 <critical_path+0x54>
  400c54:	90000000 	adrp	x0, 400000 <_init-0x578>
  400c58:	91392000 	add	x0, x0, #0xe48
  400c5c:	97fffe6d 	bl	400610 <printf@plt>
  400c60:	52800020 	mov	w0, #0x1                   	// #1
  400c64:	b9004fa0 	str	w0, [x29, #76]
  400c68:	1400002e 	b	400d20 <critical_path+0x220>
  400c6c:	f9400fa1 	ldr	x1, [x29, #24]
  400c70:	b9804fa0 	ldrsw	x0, [x29, #76]
  400c74:	9100dc00 	add	x0, x0, #0x37
  400c78:	d37cec00 	lsl	x0, x0, #4
  400c7c:	8b000020 	add	x0, x1, x0
  400c80:	f9400800 	ldr	x0, [x0, #16]
  400c84:	f90023a0 	str	x0, [x29, #64]
  400c88:	14000020 	b	400d08 <critical_path+0x208>
  400c8c:	f94023a0 	ldr	x0, [x29, #64]
  400c90:	b9400000 	ldr	w0, [x0]
  400c94:	b9003ba0 	str	w0, [x29, #56]
  400c98:	f94023a0 	ldr	x0, [x29, #64]
  400c9c:	b9400400 	ldr	w0, [x0, #4]
  400ca0:	b90037a0 	str	w0, [x29, #52]
  400ca4:	f9400fa0 	ldr	x0, [x29, #24]
  400ca8:	b9804fa1 	ldrsw	x1, [x29, #76]
  400cac:	b8617800 	ldr	w0, [x0, x1, lsl #2]
  400cb0:	b90033a0 	str	w0, [x29, #48]
  400cb4:	f9400fa1 	ldr	x1, [x29, #24]
  400cb8:	b9803ba0 	ldrsw	x0, [x29, #56]
  400cbc:	91002000 	add	x0, x0, #0x8
  400cc0:	d37ef400 	lsl	x0, x0, #2
  400cc4:	8b000020 	add	x0, x1, x0
  400cc8:	b9400801 	ldr	w1, [x0, #8]
  400ccc:	b94037a0 	ldr	w0, [x29, #52]
  400cd0:	4b000020 	sub	w0, w1, w0
  400cd4:	b9002fa0 	str	w0, [x29, #44]
  400cd8:	b94033a1 	ldr	w1, [x29, #48]
  400cdc:	b9402fa0 	ldr	w0, [x29, #44]
  400ce0:	6b00003f 	cmp	w1, w0
  400ce4:	540000c1 	b.ne	400cfc <critical_path+0x1fc>  // b.any
  400ce8:	90000000 	adrp	x0, 400000 <_init-0x578>
  400cec:	91398000 	add	x0, x0, #0xe60
  400cf0:	b9403ba2 	ldr	w2, [x29, #56]
  400cf4:	b9404fa1 	ldr	w1, [x29, #76]
  400cf8:	97fffe46 	bl	400610 <printf@plt>
  400cfc:	f94023a0 	ldr	x0, [x29, #64]
  400d00:	f9400400 	ldr	x0, [x0, #8]
  400d04:	f90023a0 	str	x0, [x29, #64]
  400d08:	f94023a0 	ldr	x0, [x29, #64]
  400d0c:	f100001f 	cmp	x0, #0x0
  400d10:	54fffbe1 	b.ne	400c8c <critical_path+0x18c>  // b.any
  400d14:	b9404fa0 	ldr	w0, [x29, #76]
  400d18:	11000400 	add	w0, w0, #0x1
  400d1c:	b9004fa0 	str	w0, [x29, #76]
  400d20:	b9404fa0 	ldr	w0, [x29, #76]
  400d24:	7100241f 	cmp	w0, #0x9
  400d28:	54fffa2d 	b.le	400c6c <critical_path+0x16c>
  400d2c:	52800140 	mov	w0, #0xa                   	// #10
  400d30:	97fffe3c 	bl	400620 <putchar@plt>
  400d34:	d503201f 	nop
  400d38:	a8c57bfd 	ldp	x29, x30, [sp], #80
  400d3c:	d65f03c0 	ret

0000000000400d40 <main>:
  400d40:	d110c3ff 	sub	sp, sp, #0x430
  400d44:	a9007bfd 	stp	x29, x30, [sp]
  400d48:	910003fd 	mov	x29, sp
  400d4c:	910063a0 	add	x0, x29, #0x18
  400d50:	97fffe77 	bl	40072c <adjacency>
  400d54:	910063a0 	add	x0, x29, #0x18
  400d58:	97fffed3 	bl	4008a4 <topsort>
  400d5c:	910063a0 	add	x0, x29, #0x18
  400d60:	97ffff68 	bl	400b00 <critical_path>
  400d64:	d503201f 	nop
  400d68:	a9407bfd 	ldp	x29, x30, [sp]
  400d6c:	9110c3ff 	add	sp, sp, #0x430
  400d70:	d65f03c0 	ret
  400d74:	00000000 	.inst	0x00000000 ; undefined

0000000000400d78 <__libc_csu_init>:
  400d78:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400d7c:	910003fd 	mov	x29, sp
  400d80:	a901d7f4 	stp	x20, x21, [sp, #24]
  400d84:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0x10184>
  400d88:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0x10184>
  400d8c:	91374294 	add	x20, x20, #0xdd0
  400d90:	913722b5 	add	x21, x21, #0xdc8
  400d94:	a902dff6 	stp	x22, x23, [sp, #40]
  400d98:	cb150294 	sub	x20, x20, x21
  400d9c:	f9001ff8 	str	x24, [sp, #56]
  400da0:	2a0003f6 	mov	w22, w0
  400da4:	aa0103f7 	mov	x23, x1
  400da8:	9343fe94 	asr	x20, x20, #3
  400dac:	aa0203f8 	mov	x24, x2
  400db0:	97fffdf2 	bl	400578 <_init>
  400db4:	b4000194 	cbz	x20, 400de4 <__libc_csu_init+0x6c>
  400db8:	f9000bb3 	str	x19, [x29, #16]
  400dbc:	d2800013 	mov	x19, #0x0                   	// #0
  400dc0:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  400dc4:	aa1803e2 	mov	x2, x24
  400dc8:	aa1703e1 	mov	x1, x23
  400dcc:	2a1603e0 	mov	w0, w22
  400dd0:	91000673 	add	x19, x19, #0x1
  400dd4:	d63f0060 	blr	x3
  400dd8:	eb13029f 	cmp	x20, x19
  400ddc:	54ffff21 	b.ne	400dc0 <__libc_csu_init+0x48>  // b.any
  400de0:	f9400bb3 	ldr	x19, [x29, #16]
  400de4:	a941d7f4 	ldp	x20, x21, [sp, #24]
  400de8:	a942dff6 	ldp	x22, x23, [sp, #40]
  400dec:	f9401ff8 	ldr	x24, [sp, #56]
  400df0:	a8c47bfd 	ldp	x29, x30, [sp], #64
  400df4:	d65f03c0 	ret

0000000000400df8 <__libc_csu_fini>:
  400df8:	d65f03c0 	ret

Disassembly of section .fini:

0000000000400dfc <_fini>:
  400dfc:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  400e00:	910003fd 	mov	x29, sp
  400e04:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400e08:	d65f03c0 	ret
